In conventional DRAM memory cells having cylindrical stacked-cell capacitors, as shown FIG. 62, can be used to increase the capacitance of each memory cell. A gate oxide film 5 is formed in an element region separated by a SiO.sub.2 field film 2 on a p-type silicon substrate 1. A word line WL composed of polysilicon and an SiO.sub.2 layer 6 are formed on it, and n.sup.+ -type semiconductor regions 3 (source) and 4 (drain) are formed by the self-alignment method with the word line WL used as a mask.
Then an SiO.sub.2 passivation layer 7, an Si.sub.3 N.sub.4 substrate protection layer 8, and an SiO.sub.2 layer 9 are successively formed over the entire surface. A polysilicon layer 11 (storage node) is formed to include a contact hole 10, which is formed on a part of the passivation layer down to the n.sup.+ -type source region 3, and to be connected to source region 3. A cylindrical polysilicon layer 13 is formed on polysilicon layer 11, and a bottom capacitor electrode is formed from polysilicon layers 11 and 13. Furthermore, a dielectric film, for example a Si.sub.3 N.sub.4 film 15, is deposited over the entire surface of polysilicon layer 11, and a top capacitor electrode (plate electrode) such as a polysilicon layer 16 is formed on the Si.sub.3 N.sub.4 layer.
Thus, a capacitor cap, having top and bottom capacitor electrodes 16, 11, and 13 and dielectric film 15, having increased capacitance due to screen type polysilicon layer 13 is connected to source region 3.
An interlayer insulating layer, for example, silicate glass layer (BPSG layer) 36 with doped boron and phosphorus, is deposited on top electrode 16 by the CVD method, and a contact hole 49 is formed in it down to n.sup.+ -type drain region 4. By adhering a bit line BL to contact hole 49 via polysilicon layer 50, a memory cell (M-CEL) for a 16 Mb or 64 Mb DRAM, for example, can be fabricated.
As shown in FIG. 55, this type of DRAM generally has a peripheral circuit portion PC and a memory cell array portion MA having many memory cells M-CEL. After an insulating BPSG layer 36 is formed on portion MA and peripheral circuit portion PC according to a process to be explained below, and wiring such as a bit line BL, etc., is applied. On one principal surface of p-type silicon substrate 1, many memory cells M-CELL (cell height about 1.2 .mu.m, word line spacing about 0.4 .mu.m, word line height about 3500 .ANG.) with a stacked-cell capacitor cap as shown in FIG. 62 are formed into a memory array in a portion MA and MOS transistors TR for input/output circuits are formed in a peripheral circuit portion PC. Transistors TR are composed, for example, of a structure provided with a polysilicon gate electrode 20 between n.sup.+ -type source region 23 and n.sup.+ -type drain region 24 via gate oxide film 5.
Next, as shown in FIG. 56, a BPSG layer 36 is deposited to a thickness about 0.6 .mu.m over the entire surface of substrate 1 by the CVD method. At the surface of this deposited layer 36, memory cells M-CELL are formed between word lines WL. In accordance with the thickness of the word lines and height of the cell capacitor cap, steps 21 are created in portion MA. Because a high structure such as a screen structure does not exist outside of the terminating part in portion MA (the distance between gate electrode 20 and word line WL of the memory cell is about 4 .mu.m), a step 22 steeper than step 21 is created between portion MA and peripheral circuit portion PC.
We call step 21 in portion MA a "local step"; this is a step between multiple, relatively close word lines WL (or between the cells). Normally it is created when the distance between the word lines or between adjacent wiring is less than 10 .mu.m.
We call larger step 22 between portion MA and peripheral circuit portion PC a "global step" in the present specification. This is quite steep and normally created when the distance between the word lines or between adjacent wiring is over 10 .mu.m (however, it may be less than 10 .mu.m according to the case).
Even in peripheral circuit portion PC, a step 25 may be created between gate electrodes 20 and 20 or on the gate electrode 20 side. But this has a smaller height difference than global step 22 (however, it may have a height difference greater than or equal to local step 21). Steps 21 and 22 and 25 must be eliminated and flattened in order to provide wiring reliably on BPSG layer 36. For this purpose, BPSG layer 36 is caused to reflow by annealing for 10 min at 900.degree. C. in the state of FIG. 56.
However, while local step 21 in portion MA is essentially eliminated, step 25 in portion PC becomes a gradual slope like 35, and the steepness of global step 22 becomes reduced. However, as shown in FIG. 57, it is difficult to flatten out the large height difference in the vicinity of global step 22. So a global step 32 with height difference about 1.2 .mu.m is left between portion MA and portion PC.
Then in FIG. 58, a contact hole 49 is formed at a prescribed location in BPSG layer 36 and prescribed wiring, in particular, a bit line BL is formed via a polysilicon layer 50. Due to the large step differences at global step 32, breaks and short circuits tend to form in wiring BL during photolithography. When, for example, a positive photoresist is thickly deposited where the breaks occur, exposure to the bottom part of the photoresist is not possible, and short circuits occur or the exposure part of the photoresist that should not be exposed is exposed due to the irregular reflection caused by the slope of step 32, etc., changes occur in the pattern width of the wiring formed by etching using a photoresist with pattern as a mask, and there may be corresponding breaks in the wiring.
Also, when aluminum is used for wiring BL, breaks may be generated during use in the step part due to so-called electromigration even if breaks are not generated during fabrication.
The spin-coating of SOG (spin-on glass) which is different from the aforementioned method is used to eliminate the step and to produce the wiring reliably. SiO.sub.2 insulating layer 166 is provided is accordance with the plasma CVD method as indicated by the segmented line in FIG. 62. Insulating layer 166 formed in accordance with the plasma CVD method, which has the advantage of superior insulating properties, precise formation, and the ability to be formed at low temperatures, is used mainly for the flattening of the metal wiring; high-temperature annealing to create reflow, as with BPSG, is not executed. Thereafter, the surface is made flat by spin coating SOG 167 on insulating layer 166. This structure is fabricated according to the procedure shown in FIG. 59-61.
As shown in FIG. 59, SiO.sub.2 insulating layer 166 is deposited to a thickness of 0.6 .mu.m over the entire surface of substrate 1 in accordance to the plasma CVD method. In the surface of the deposited layer 166, memory cells M-CELL are formed in accordance with the height of cell capacitor cap, and the thickness of word line WL, etc., and local step 21 is created in portion MA; on the other hand, a projecting structure such as a screen does not exist on the outside of the terminating part of portion MA (the distance between gate electrode 20 and word line WL of the memory cell is about 4 .mu.m) so that global step 22 steeper than step 21 is created between portion PC and portion MA.
Then SOG 167 is spin-coated over the entire surface of insulating layer 166 as shown in FIG. 60. In this state, the top of local step 21 becomes flat according to insulation layer 167, but step 32' greater than 1.0 .mu.m is formed on global step 22 according to the height difference of the two sides.
When bit line BL is deposited on SOG layer 167 as shown in FIG. 61, breaks and short circuits in wiring BL occur easily on step 321 for the same reasons explained in connection with FIG. 58.
Thus, the aforementioned methods decrease the reliability of the wiring, limit the refinement of the wiring width and pitch, and are very disadvantageous for the fabrication of high-integrated semiconductors.
The object of our invention is to provide a semiconductor device manufacturing method in which the flattening of the insulating layer, such as the BPSG layer or SOG layer, can be executed easily, and the wiring, etc., can be formed with good reliability and with a wide tolerance in the subsequent processes.